27#ifndef LIBWS_MEMORY_H_
28#define LIBWS_MEMORY_H_
46#define ws_iram __wf_iram
53#define ws_sram __wf_sram
62#define ws_rom __wf_rom
72#define ws_ptr_offset(x) ((uint16_t) (x))
77#define ws_ptr_segment(x) FP_SEG(x)
82#define ws_ptr_far(seg, ofs) MK_FP(seg, ofs)
88 return ((((uint32_t) src) >> 12) & 0xFFFF0) + ((uint16_t) ((uint32_t) src));
101#define WS_IRAM_MEM ((uint8_t ws_iram*) 0x00000000)
105#define WS_SRAM_MEM ((uint8_t ws_sram*) 0x10000000)
109#define WS_ROM0_MEM ((uint8_t __far*) 0x20000000)
113#define WS_ROM1_MEM ((uint8_t __far*) 0x30000000)
115#ifdef LIBWS_USE_EXTBANK
120 asm volatile(
"" :::
"memory");
121 volatile ws_bank_t old_bank = inportw(port);
122 outportw(port, new_bank);
123 asm volatile(
"" :::
"memory");
127static inline void _ws_bank_set(uint8_t port,
ws_bank_t new_bank) {
128 asm volatile(
"" :::
"memory");
129 outportw(port, new_bank);
130 asm volatile(
"" :::
"memory");
133#define _ws_bank_ram_port WS_CART_EXTBANK_RAM_PORT
134#define _ws_bank_rom0_port WS_CART_EXTBANK_ROM0_PORT
135#define _ws_bank_rom1_port WS_CART_EXTBANK_ROM1_PORT
136#define _ws_bank_roml_port WS_CART_EXTBANK_ROML_PORT
143 asm volatile(
"" :::
"memory");
144 volatile ws_bank_t old_bank = inportb(port);
145 outportb(port, new_bank);
146 asm volatile(
"" :::
"memory");
150static inline void _ws_bank_set(uint8_t port,
ws_bank_t new_bank) {
151 asm volatile(
"" :::
"memory");
152 outportb(port, new_bank);
153 asm volatile(
"" :::
"memory");
156#define _ws_bank_ram_port WS_CART_BANK_RAM_PORT
157#define _ws_bank_rom0_port WS_CART_BANK_ROM0_PORT
158#define _ws_bank_rom1_port WS_CART_BANK_ROM1_PORT
159#define _ws_bank_roml_port WS_CART_BANK_ROML_PORT
164#define ws_bank_within_(var, loc, prev_bank, ...) \
166 extern const void __bank_ ## var; \
167 ws_bank_t prev_bank = ws_bank_ ## loc ## _save((unsigned int) (&__bank_ ## var)); \
169 ws_bank_ram_restore(prev_bank); \
172#define ws_bank_with_(var, loc, prev_bank, ...) \
174 ws_bank_t prev_bank = ws_bank_ ## loc ## _save((unsigned int) var); \
176 ws_bank_ram_restore(prev_bank); \
186#define ws_bank_ram_save(new_bank) _ws_bank_save(_ws_bank_ram_port, (new_bank))
193#define ws_bank_ram_set(new_bank) _ws_bank_set(_ws_bank_ram_port, (new_bank))
194#define ws_bank_ram_restore ws_bank_ram_set
210#define ws_bank_within_ram(var, ...) ws_bank_within_(var, ram WF_MACRO_CONCAT(_wf_bank_, __COUNTER__), __VA_ARGS__)
225#define ws_bank_with_ram(bank, ...) ws_bank_with_(bank, ram, WF_MACRO_CONCAT(_wf_bank_, __COUNTER__), __VA_ARGS__)
233#define ws_bank_rom0_save(new_bank) _ws_bank_save(_ws_bank_rom0_port, (new_bank))
240#define ws_bank_rom0_set(new_bank) _ws_bank_set(_ws_bank_rom0_port, (new_bank))
241#define ws_bank_rom0_restore ws_bank_rom0_set
257#define ws_bank_within_rom0(var, ...) ws_bank_within_(var, rom0, WF_MACRO_CONCAT(_wf_bank_, __COUNTER__), __VA_ARGS__)
272#define ws_bank_with_rom0(bank, ...) ws_bank_within_(bank, rom0, WF_MACRO_CONCAT(_wf_bank_, __COUNTER__), __VA_ARGS__)
280#define ws_bank_rom1_save(new_bank) _ws_bank_save(_ws_bank_rom1_port, (new_bank))
287#define ws_bank_rom1_set(new_bank) _ws_bank_set(_ws_bank_rom1_port, (new_bank))
288#define ws_bank_rom1_restore ws_bank_rom1_set
304#define ws_bank_within_rom1(var, ...) ws_bank_within_(var, rom1, WF_MACRO_CONCAT(_wf_bank_, __COUNTER__), __VA_ARGS__)
319#define ws_bank_with_rom1(bank, ...) ws_bank_with_(bank, rom1, WF_MACRO_CONCAT(_wf_bank_, __COUNTER__), __VA_ARGS__)
327#define ws_bank_roml_save(new_bank) _ws_bank_save(_ws_bank_roml_port, (new_bank))
334#define ws_bank_roml_set(new_bank) _ws_bank_set(_ws_bank_roml_port, (new_bank))
335#define ws_bank_roml_restore ws_bank_roml_set
351#define ws_bank_within_roml(var, ...) ws_bank_within_(var, roml, WF_MACRO_CONCAT(_wf_bank_, __COUNTER__), __VA_ARGS__)
366#define ws_bank_with_roml(bank, ...) ws_bank_with_(bank, roml, WF_MACRO_CONCAT(_wf_bank_, __COUNTER__), __VA_ARGS__)
static const void ws_far * ws_ptr_from_linear(uint32_t src)
uint8_t ws_bank_t
Type indicating a bank index.
static uint32_t ws_ptr_to_linear(const void ws_far *src)
#define ws_ptr_far(seg, ofs)