libws libws
WSwan hardware library for the Wonderful toolchain
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memory.h
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1/*
2 * Copyright (c) 2022 Adrian "asie" Siekierka
3 *
4 * This software is provided 'as-is', without any express or implied
5 * warranty. In no event will the authors be held liable for any damages
6 * arising from the use of this software.
7 *
8 * Permission is granted to anyone to use this software for any purpose,
9 * including commercial applications, and to alter it and redistribute it
10 * freely, subject to the following restrictions:
11 *
12 * 1. The origin of this software must not be misrepresented; you must not
13 * claim that you wrote the original software. If you use this software
14 * in a product, an acknowledgment in the product documentation would be
15 * appreciated but is not required.
16 *
17 * 2. Altered source versions must be plainly marked as such, and must not be
18 * misrepresented as being the original software.
19 *
20 * 3. This notice may not be removed or altered from any source distribution.
21 */
22
26
27#ifndef LIBWS_MEMORY_H_
28#define LIBWS_MEMORY_H_
29
30#include <stdbool.h>
31#include <stdint.h>
32#include <wonderful.h>
33#include "ports.h"
34#include "util.h"
35
40
46#define ws_iram __wf_iram
47
53#define ws_sram __wf_sram
54
62#define ws_rom __wf_rom
63
67#define ws_far __far
68
72#define ws_ptr_offset(x) ((uint16_t) (x))
73
77#define ws_ptr_segment(x) FP_SEG(x)
78
82#define ws_ptr_far(seg, ofs) MK_FP(seg, ofs)
83
87static inline uint32_t ws_ptr_to_linear(const void ws_far *src) {
88 return ((((uint32_t) src) >> 12) & 0xFFFF0) + ((uint16_t) ((uint32_t) src));
89}
90
94static inline const void ws_far *ws_ptr_from_linear(uint32_t src) {
95 return ws_ptr_far(src >> 4, src & 0xF);
96}
97
101#define WS_IRAM_MEM ((uint8_t ws_iram*) 0x00000000)
105#define WS_SRAM_MEM ((uint8_t ws_sram*) 0x10000000)
109#define WS_ROM0_MEM ((uint8_t __far*) 0x20000000)
113#define WS_ROM1_MEM ((uint8_t __far*) 0x30000000)
114
115#ifdef LIBWS_USE_EXTBANK
116typedef uint16_t ws_bank_t;
117
119static inline ws_bank_t _ws_bank_save(uint8_t port, ws_bank_t new_bank) {
120 asm volatile("" ::: "memory");
121 volatile ws_bank_t old_bank = inportw(port);
122 outportw(port, new_bank);
123 asm volatile("" ::: "memory");
124 return old_bank;
125}
126
127static inline void _ws_bank_set(uint8_t port, ws_bank_t new_bank) {
128 asm volatile("" ::: "memory");
129 outportw(port, new_bank);
130 asm volatile("" ::: "memory");
131}
132
133#define _ws_bank_ram_port WS_CART_EXTBANK_RAM_PORT
134#define _ws_bank_rom0_port WS_CART_EXTBANK_ROM0_PORT
135#define _ws_bank_rom1_port WS_CART_EXTBANK_ROM1_PORT
136#define _ws_bank_roml_port WS_CART_EXTBANK_ROML_PORT
138#else
139typedef uint8_t ws_bank_t;
140
142static inline ws_bank_t _ws_bank_save(uint8_t port, ws_bank_t new_bank) {
143 asm volatile("" ::: "memory");
144 volatile ws_bank_t old_bank = inportb(port);
145 outportb(port, new_bank);
146 asm volatile("" ::: "memory");
147 return old_bank;
148}
149
150static inline void _ws_bank_set(uint8_t port, ws_bank_t new_bank) {
151 asm volatile("" ::: "memory");
152 outportb(port, new_bank);
153 asm volatile("" ::: "memory");
154}
155
156#define _ws_bank_ram_port WS_CART_BANK_RAM_PORT
157#define _ws_bank_rom0_port WS_CART_BANK_ROM0_PORT
158#define _ws_bank_rom1_port WS_CART_BANK_ROM1_PORT
159#define _ws_bank_roml_port WS_CART_BANK_ROML_PORT
161#endif
162
164#define ws_bank_within_(var, loc, prev_bank, ...) \
165 { \
166 extern const void __bank_ ## var; \
167 ws_bank_t prev_bank = ws_bank_ ## loc ## _save((unsigned int) (&__bank_ ## var)); \
168 __VA_ARGS__ \
169 ws_bank_ram_restore(prev_bank); \
170 }
171
172#define ws_bank_with_(var, loc, prev_bank, ...) \
173 { \
174 ws_bank_t prev_bank = ws_bank_ ## loc ## _save((unsigned int) var); \
175 __VA_ARGS__ \
176 ws_bank_ram_restore(prev_bank); \
177 }
179
186#define ws_bank_ram_save(new_bank) _ws_bank_save(_ws_bank_ram_port, (new_bank))
187
193#define ws_bank_ram_set(new_bank) _ws_bank_set(_ws_bank_ram_port, (new_bank))
194#define ws_bank_ram_restore ws_bank_ram_set
195
210#define ws_bank_within_ram(var, ...) ws_bank_within_(var, ram WF_MACRO_CONCAT(_wf_bank_, __COUNTER__), __VA_ARGS__)
211
225#define ws_bank_with_ram(bank, ...) ws_bank_with_(bank, ram, WF_MACRO_CONCAT(_wf_bank_, __COUNTER__), __VA_ARGS__)
226
233#define ws_bank_rom0_save(new_bank) _ws_bank_save(_ws_bank_rom0_port, (new_bank))
234
240#define ws_bank_rom0_set(new_bank) _ws_bank_set(_ws_bank_rom0_port, (new_bank))
241#define ws_bank_rom0_restore ws_bank_rom0_set
242
257#define ws_bank_within_rom0(var, ...) ws_bank_within_(var, rom0, WF_MACRO_CONCAT(_wf_bank_, __COUNTER__), __VA_ARGS__)
258
272#define ws_bank_with_rom0(bank, ...) ws_bank_within_(bank, rom0, WF_MACRO_CONCAT(_wf_bank_, __COUNTER__), __VA_ARGS__)
273
280#define ws_bank_rom1_save(new_bank) _ws_bank_save(_ws_bank_rom1_port, (new_bank))
281
287#define ws_bank_rom1_set(new_bank) _ws_bank_set(_ws_bank_rom1_port, (new_bank))
288#define ws_bank_rom1_restore ws_bank_rom1_set
289
304#define ws_bank_within_rom1(var, ...) ws_bank_within_(var, rom1, WF_MACRO_CONCAT(_wf_bank_, __COUNTER__), __VA_ARGS__)
305
319#define ws_bank_with_rom1(bank, ...) ws_bank_with_(bank, rom1, WF_MACRO_CONCAT(_wf_bank_, __COUNTER__), __VA_ARGS__)
320
327#define ws_bank_roml_save(new_bank) _ws_bank_save(_ws_bank_roml_port, (new_bank))
328
334#define ws_bank_roml_set(new_bank) _ws_bank_set(_ws_bank_roml_port, (new_bank))
335#define ws_bank_roml_restore ws_bank_roml_set
336
351#define ws_bank_within_roml(var, ...) ws_bank_within_(var, roml, WF_MACRO_CONCAT(_wf_bank_, __COUNTER__), __VA_ARGS__)
352
366#define ws_bank_with_roml(bank, ...) ws_bank_with_(bank, roml, WF_MACRO_CONCAT(_wf_bank_, __COUNTER__), __VA_ARGS__)
367
369
370#endif /* LIBWS_MEMORY_H_ */
static const void ws_far * ws_ptr_from_linear(uint32_t src)
Definition memory.h:94
#define ws_far
Definition memory.h:67
uint8_t ws_bank_t
Type indicating a bank index.
Definition memory.h:139
static uint32_t ws_ptr_to_linear(const void ws_far *src)
Definition memory.h:87
#define ws_ptr_far(seg, ofs)
Definition memory.h:82