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--- wswan:guide:optimization_v30mz [2024/02/17 18:53] – created asie
+++ wswan:guide:optimization_v30mz [2024/02/17 20:11] (current) – asie
@@ Line 3: / Line 3: @@
 While the V30MZ is an 80186-compatible CPU, its instruction timings differ wildly from common expectations and are more reflective of its 1990s-era design:
-  * ''MUL'' is very fast on this CPU, taking 3-4 cycles. As a result, "shift plus add" ladders will almost always be equal in performance on slower.
+  * ''MUL'' is very fast on this CPU, taking 3-4 cycles. As a result, "shift plus add" ladders will almost always be slower or, at best, equal in performance.
+  * Using ''XCHG'' over ''PUSH/POP'' (and ''XCHG AX, reg'' over ''MOV AX, reg'') is a popular pattern on the 8088/8086 due to the speed benefit. However, on the V30MZ, that is not the case:
+    * ''XCHG'' on V30MZ always takes 3 cycles.
+    * ''PUSH'' and ''POP'' take 1 cycle each for general registers. This means that ''PUSH/POP'' will be one cycle faster.
+    * While ''MOV AX, reg'' is one byte larger than ''XCHG AX, reg'', it also only takes 1 cycle.
   * ''XLAT'' takes 5 cycles. Many simple CPU operations (such as ''SHR reg, 4'' or ''MUL reg'' - both taking 3 cycles) can actually be faster!
 TODO: Expand this list.